As the trend to provide substantially increased circuit functionality on an integrated circuit die continues, the so-called system-on-chip (SOC) integrated circuit configuration has rapidly gained popularity in almost all application fields of an integrated circuit. It has hence become necessary to form a tremendously large number of transistors on an integrated circuit die. In the meantime, forming a complex electronic system on an integrated circuit die results in the need for a large number of input/output (I/O) connections between an integrated circuit die and the rest of the electronic system of which the integrated circuit is a part. New packaging technologies, such as flip-chip ball grid array (BGA) have been developed to meet this need. In a flip-chip BGA package, a large number of I/O connection terminals (solder balls) are disposed in a two dimensional array over a substantial portion of a major surface of an integrated circuit die. The die surface with solder bump array formed thereon is in turn attached to a supporting package substrate. Although flip-chip BGA packages provide a space-saving solution, other technical challenges remain to be addressed. First, the coefficient of thermal expansion of a package substrate (in general, a dielectric material) does not provide a good match with the semiconductor material of an integrated circuit die. Thermal stress could cause the solder bumps and die to tear free of the package, which casts a major reliability concern on the package of this configuration. Second, for example, as the device feature sizes in the logical part of a system-on-chip integrated circuit continue to shrink, a relatively large portion of die area will be occupied by hard-to-scale circuits such as RF circuits, wherein large value capacitors and inductors are usually required for circuit function. This phenomenon will eventually lead to a point where further scaling down of die size will become extremely difficult, if not impossible. The other issue facing the SOC configuration is the increasing challenge on SOC design, where, for example, integrating digital and RF functions on a same die has made circuit modeling much more complicated and on-chip signal interference difficult to resolve. This and other challenges have lead to the adoption of an interposer in an electronic package, where a structure made of material having a matching coefficient of thermal expansion to a semiconductor die is provided between an integrated circuit die and package substrate. Circuit functions involving large size passive/active devices can also be formed in an interposer and coupled to an integrated circuit die attached to it.
Shown in FIG. 1 is a schematic section view of an integrated circuit die coupled to a prior art silicon interposer and the silicon interposer coupled to a supporting package substrate. In FIG. 1 a silicon-based integrated circuit die 10 is attached to a first side of a silicon interposer 30. Solder bumps 15 are used to provide electrical connection between integrated circuit die 10 and silicon interposer 30. A second side of silicon interposer 30 is attached to package substrate 50 by solder balls 55. Solder balls 55 provides electrical connection between silicon interposer 30 and package substrate 50, which in turn makes electrical connection to a printed circuit board (PCB, not shown) through package leads 65. A silicon interposer provides a matching coefficient of thermal expansion to the integrated circuit die in order to reduce the potential solder failure between the integrated circuit die and the package substrate caused by thermal stresses. A silicon interposer also provides adaptation between smaller contact pads with reduced pitch on an integrated circuit die and larger contact pads with increased pitch on a package substrate. In addition, various circuit elements may be incorporated into a silicon interposer. These circuit elements may be active, passive, or a combination of active and passive elements.
FIG. 2 is a schematic section view of a silicon interposer in accordance with FIG. 1. Silicon interposer 30 includes silicon substrate 33, insulating material 35, solder bumps 15, solder balls 55, interconnections 32, and through-silicon-vias 34. In general, silicon substrate 33 is similar to the doped silicon substrate used to form integrated circuit die 10, wherein active semiconductor devices can be formed. Insulating material 35 can be oxide dielectric or other dielectric materials in which interconnection layers may be formed from a conductive material such as aluminum and copper. Solder bumps 15 having tighter pitch are adapted for connection to integrated circuit die 10, while solder balls 55 having wider pitch are adapted for connection to package substrate 50. Through-silicon-vias 34 provide direct electrically conductive pathways between solder bumps 15 and solder balls 55. It can be seen that passive devices, such as capacitor 41, resistor 42, inductor 43 and active devices, such as MOSFET 44 can be formed in insulating material 35 and/or silicon substrate 33. These devices are electrically connected to the integrated circuit die 10 through solder bumps 15. Active and passive devices integrated in an interposer can provide necessary circuit functions to an integrated circuit die and offer advantageous features which would otherwise not be possible if placing these devices in the integrated circuit die or on the printed circuit board an electronic package attached to. As an example, placing a decoupling capacitor into an integrated circuit die requires dramatic increase on die size, while placing it on a printed circuit board causes undesirable parasitic inductance associated with metal traces and package leads. These and other drawbacks are generally overcome by placing a decoupling capacitor in an interposer closer to an integrated circuit die in a same electronic package.
However, technical drawback remains in a prior art interposer. In designing and manufacturing a prior art interposer, an integrated circuit design (user, customer) must first decide what circuit functions and device parameters are to be expected from an interposer, through system level modeling and prototyping. A package design team is usually dedicated in designing a custom interposer on which active/passive devices of fixed values are formed to match a specific integrated circuit product. Due to this nature, an electronic package involving a prior art interposer is in general very costly to design and manufacture. In practice, only integrated circuit products of large market volume can justify the cost relating to the interposer containing package scheme. This drawback has hindered prior art interposers from quicker and wider adoption in electronic packaging. In view of this and others problems in making and using a prior art interposer, there is a need for a standard, programmable interposer which can be designed and manufactured as a standard product in large scale, which can supply specific circuit function to a custom integrated circuit product, when appropriately programmed.